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SystemVerilog for RTL Design
San Jose 1762 Technology dr.suite 228
8 years, 7 months
Ad ID:ADOIST-1269435
Category:Services
Subcategory:Education
Description
SystemVerilog for RTL Design This hands-on program prepares the student for digital design and debug at the RTL level. During the program, students will first review key Verilog building blocks. They will then progress to SystemVerilog enhancements, including: structures, arrays, enumerations, and bus interface blocks. In each step-by-step lab, students will synthesize these high-level constructs into nanometer gate logic for ASICs or FPGAs, using Synopsys Design Compiler or Synplify Pro. Coding tips for high speed and low power will be highlighted. Labs will culminate with a self-paced design and debug project. The program includes writing block-level testbenches in SystemVerilog, and embedding assertions directly in the RTL code. As IC chips and IP cores get more complex, exposure to RTL design and debug using SystemVerilog enhancements is becoming more and more of a necessary skill.
We welcome and accept: Corporate Tuition Reimbursement, Workers Compensation, California Training Benefit (CTB), Trade Adjustment Act (TAA), Workforce Investment Act (WIA), Vocational Rehab, and more... For more information please contact Silicon Valley Polytechnic Institute; info@svpti.com or call 408-436-3000.
San Jose, 3163 Loma Verde Drive, Unit 10, San Jose, CA 951
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